Gallery
What you can draw with TimeGen 5.
These are exported straight from TimeGen 5. Each one links to the part of the manual that shows how it was made.
DDR read timing
Differential clock, DQS strobe, and DQ data valid on both clock edges.
How it's drawn →
SPI timing diagram
Serial interface timing: CS, SCLK, SDI, SDO, LDAC, and VOUT.
How it's drawn →
I2C start and stop
SDA and SCL with a start condition, address, and stop.
How it's drawn →
Reset timing
Supply ramp, reset asserted low, and the minimum reset pulse width before the device is ready.
How it's drawn →
DDR4 activate timing
Command, bank group, bank, and address buses, with tRRD_S and tRRD_L spacing between activates.
How it's drawn →